HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 276

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 X/Y Memory
6.3.3
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If
the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC). In a program that
requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The
relationship described above is summarized in table 6.2.
Table 6.2
Note:
6.3.4
In sleep mode, I bus master modules such as the DMAC cannot access the X/Y memory.
Page 216 of 1414
CCR1.CE
0
0
1
1
A: Accessible (recommended)
B: Accessible
C: Accessible (Note that MMU page attribute must be specified as cache disabled by
X: Not accessible
MMU and Cache Settings
Sleep Mode
clearing the C bit to 0.)
Setting
MMU and Cache Settings
MMUCR.AT
0
1
0
1
P0, U0
B
B
X
C
Virtual Address Space and Access Enabled or Disabled
P1
B
B
X
X
A
A
A
P2, Uxy
A
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
P3
B
B
X
C
Sep 21, 2010