HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 278

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Exception Handling
Figure 7.1 shows the bit configuration of each register.
7.1.1
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
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Bit
31 to 10 ⎯
9 to 2
1, 0
TRAPA Exception Register (TRA)
TRA
Bit Name
⎯
31
31
31
31
31
Initial
Value
⎯
⎯
⎯
Figure 7.1 Register Bit Configuration
R/W
R
R/W
R
0
0
0
0
TEA
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
12 11
12 11
12 11
10 9
EXPEVT
INTEVT
INTEVT2
TRA
2 1 0
0
0
0
0
0
TRA
EXPEVT
INTEVT
INTEVT2
TEA
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010