HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 285

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Table 7.1
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Exception
Type
Reset
(asynchro-
nous)
General
exception
events
(synchro-
nous)
Current
Instruction Exception Event
Aborted
Re-executed
Re-executed
Completed
Exception Event Vectors
Power-on reset
Manual reset
User break(before
instruction execution)
CPU address error
(instruction access) *
TLB miss
(instruction access) *
TLB invalid (instruction
access)*
TLB protection violation
(instruction access)*
Illegal general instruction
exception
Illegal slot
instruction exception
CPU address error
(data access)*
TLB miss
(data access)*
TLB invalid
(data access)*
TLB protection violation
(data access)*
Initial page write
(data access)*
Unconditional trap
(TRAPA instruction)
User breakpoint (After
instruction execution,
address)
4
*
5
4
4
4
4
4
*
*
*
*
5
5
5
5
4
4
4
*
*
5
5
Priority*
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Exception
Order
1
2
0
1
1-1
1-2
1-3
2
2
3
3-1
3-2
3-3
3-4
4
5
Process
at BL=1
Reset
Reset
Ignored
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Ignored
Section 7 Exception Handling
Vector
Code
H'000
H'020
H'1E0
H'0E0
H'040
H'040
H'0A0
H'180
H'1A0
H'0E0/
H'100
H'040/
H'060
H'040/
H'060
H'0A0/
H'0C0
H'080
H'160
H'1E0
Page 225 of 1414
Vector
Offset
—
—
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100