HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 434

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Bus State Controller (BSC)
(8)
This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by
clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can
be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long
period, self-refresh mode, in which the power consumption for data retention is low, can be
activated by setting both the RMODE bit and the RFSH bit to 1.
(a)
Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0] in
RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be set so
as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for
RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and
RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from
the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if
the two values are the same, a refresh request is generated and an auto-refresh is performed for the
number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the
count-up is restarted. Figure 9.25 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks
to precharged state from active state when some bank is being precharged. Then REF command is
issued in the Trr cycle after inserting idle cycles of which number is specified by the TRP[1:0]bits
in CSnWCR. A new command is not issued for the duration of the number of cycles specified by
the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must be set so as to satisfy
the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is inserted between the Tp
cycle and Trr cycle when the setting value of the TRP[1:0] bits in CSnWCR is longer than or
equal to 2 cycles.
Page 374 of 1414
Refreshing
Auto-refreshing
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010