HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 558
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 13 Power-Down Modes
13.8
13.8.1
This LSI enters hardware standby mode by driving the CA pin low. In hardware standby mode as
well as a standby mode entered by the SLEEP instruction, all modules stop other than the modules
that operate using the RTC clock.
Hardware standby mode differs from standby mode as follows:
1. Interrupts and manual reset cannot be accepted.
2. TMU does not operate.
3. RTC operates without power supply to the power supply pins other than that of RTC.
If the CA pin goes low, the operation differs according to the CPG status.
• During standby mode
• During WDT operation while the standby mode is canceled by an interrupt
• Sleep mode
Note that the CA pin must be brought low during hardware standby mode.
13.8.2
Hardware standby mode is canceled by power-on or reset. If the CA pin is pulled high while the
RESETP signal is low, clock oscillation starts. In this case, RESETP must be kept low until clock
oscillation has settled. If RESETP is then pulled high, the CPU initiates the power-on reset
processing. If an interrupt or manual reset is input, correct operation cannot be guaranteed.
Page 498 of 1414
Hardware standby mode is entered with the clock stopped.
Interrupts and manual reset cannot be accepted and TMU halts.
After standby mode is canceled and the CPU restarts operating, a transition to hardware
standby mode occurs.
After sleep mode is canceled and the CPU restarts operating, a transition to hardware standby
mode occurs.
Hardware Standby Mode
Transition to Hardware Standby Mode
Canceling the Hardware Standby Mode
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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