HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 680

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
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data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (64 – transmit trigger setting).
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt request is generated.
When the number of transmit data matches the data set in the transmit data stop register
(SCTDSR) while the transmit data stop function is used, the transmit operation is stopped and
the TSF flag in the serial status register (SCSSR) is set. When the TSIE bit in the serial control
register (SCSCR) is set to 1, transmit data stop interrupt request is generated. A common
interrupt vector is assigned to the transmit-FIFO-data-empty interrupt and the transmit-data-
stop interrupt.
The serial transmit data is sent from the TxD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is
D. Stop bit(s): One- or two-bit 1s (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If there is no transmit data, the TEND flag in the serial status register (SCSSR) is set to 1, the
stop bit is sent, and then the line goes to the mark state in which 1 is output continuously.
not output can also be selected.)
sent.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010