HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 727

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(Master output)
20.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 20.9 and 20.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
(Master output)
(Slave output)
processing
ICCKS1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
ICDRR
SCL
SDA
SDA
ICDRS
RCVD
RDRF
User
Slave Transmit Operation
Data n-1
A
[5] Read ICDRR after setting RCVD
Figure 20.8 Master Receive Mode Operation Timing (2)
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
[7] Read ICDRR,
6
and clear RCVD
Bit 1
7
Bit 0
Data n
8
Section 20 I
A/A
9
Data n
[6] Issue stop
condition
2
C Bus Interface (IIC)
Page 667 of 1414
[8] Set slave
receive mode