HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 759

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
21.3.8
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an
interrupt.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15
14
13
12
11
10
Bit Name
TDMAE
TCRDYE
TFEMPE
TDREQE
RDMAE
RCRDYE
Interrupt Enable Register (SIIER)
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as transmit
interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
1: Enables interrupts due to transmit data transfer
Receive Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The RDREQE bit can be set as receive
interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
Receive Control Data Ready Enable
requests
requests
Section 21 Serial I/O with FIFO (SIOF)
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