HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 923

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the palette memory to determine the colors, then puts the display on the LCD panel. It is possible
to connect the LCDC to the LCD module* other than microcomputer bus interface types and
NTSC/PAL types and those that apply the LVDS interface.
Note: * LCD module can be connected to the LVDS interface by using the LSI with LVDS
26.1
The LCDC has the following features.
• Panel interface
• Supports 4/8/15/16-bpp (bits per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024*
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
• Dedicated display memory is unnecessary using part of the synchronous DRAM (area 3) as the
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel's signal polarity
• Supports the selection of data formats (the endian setting for bytes, packed pixel method) by
• An interrupt can be generated at the user specified position (controlling the timing of VRAM
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
⎯ Serial interface method
⎯ Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width)*
control by 24-bit space-modulation FRC (Frame Rate Controller) with 8-bit RGB values for
reduced flicker.
VRAM to store display data of the LCDC.
register settings
update start prevents flicker)
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels (see table 26.4.)
Features
conversion LSI.
Section 26 LCD Controller (LCDC)
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Section 26 LCD Controller (LCDC)
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