HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 953

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Notes: 1. Write H'0011 to LDCNTR when starting display and H'0000 when completing display.
26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)
LDUINTR sets whether the user specified interrupt is generated, and indicates its processing state.
This interrupt is generated at the time when image data which is set by the line number register
(LDUINTLNR) in LCDC is read from VRAM.
This LCDC issues the interrupts (LCDCI): user specified interrupt by this register, memory access
interrupt by the LCDC interrupt control register (LDINTR), and OR of Vsync interrupt output.
This register and LCDC interrupt control register (LDINTR) settings affect the interrupt operation
independently.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
3 to 1
0
Bit
15 to 9 ⎯
8
2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing
Bit Name
⎯
DON
Bit Name
UINTEN
Data other than H'0011 and H'0000 must not be written to.
to the palette RAM, set bit DON2 to 1.
Initial Value
All 0
Initial Value
All 0
0
0
R/W
R
R/W
R/W
R
R/W
Description
Reserved.
These bits are always read as 0. The write value
should always be 0.
Display On
Specifies the start and stop of the LCDC display
operation.
The control sequence state can be checked by
referencing the LPS[1:0] of LDPMMR.
0: Display-off mode: LCDC is stopped
1: Display-on mode: LCDC operates
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Specified Interrupt Enable
Sets whether generate an LCDC user specified
interrupt.
0: LCDC user specified interrupt is not generated
1: LCDC user specified interrupt is generated
Section 26 LCD Controller (LCDC)
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