HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 97
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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SH7720 Group, SH7721 Group
2.1
2.1.1
This LSI supports four types of processing states: a reset state, an exception handling state, a
program execution state, and a low-power consumption state, according to the CPU processing
states.
(1)
In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and
manual reset. For details on resets, refer to section 7, Exception Handling.
In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In
manual reset, the register contents of a part of the LSI on-chip modules are retained. For details,
refer to section 37, List of Registers. The CPU internal statuses and registers are initialized both in
power-on reset and manual reset. After initialization, the program branches to address
H'A0000000 to pass control to the reset processing program to be executed.
(2)
In the exception handling state, the CPU processing flow is changed temporarily by a general
exception or interrupt exception processing. The program counter (PC) and status register (SR) are
saved in the save program counter (SPC) and save status register (SSR), respectively. The
program branches to an address obtained by adding a vector offset to the vector base register
(VBR) and passes control to the exception processing program defined by the user to be executed.
For details on reset, refer to section 7, Exception Handling.
(3)
The CPU executes programs sequentially.
(4)
The CPU stops operation to reduce power consumption. The power-down mode can be entered by
executing the SLEEP instruction. For details on the power-down mode, refer to section 13, Power-
Down Modes.
Figure 2.1 shows a status transition diagram.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Reset State
Exception Handling State
Program Execution State
Low-Power Consumption State
Processing States and Processing Modes
Processing States
Section 2 CPU
CPUS3D0S_000020020300
Page 37 of 1414
Section 2 CPU
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