HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1213

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The SH7751 Group is provided with an internal buffer for holding pre-read instructions, and
always performs pre-reading. Therefore, program code must not be located in the last 20-byte area
of any memory space. If program code is located in these areas, the memory area will be exceeded
and a bus access for instruction pre-reading may be initiated. A case in which this is a problem is
shown below.
Figure F.1 presupposes a case in which the instruction (ADD) indicated by the program counter
(PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also
assumed that the program branches to an area other than area 1 after executing the following JMP
instruction and delay slot instruction.
In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1
may be initiated.
Instruction Prefetch Side Effects
1. It is possible that an external bus access caused by an instruction prefetch may result in
2. If there is no device to reply to an external bus request caused by an instruction prefetch,
Remedies
1. These illegal instruction fetches can be avoided by using the MMU.
2. The problem can be avoided by not locating program code in the last 20 bytes of any area.
misoperation of an external device, such as a FIFO, connected to the area concerned.
hangup will occur.
Appendix F Instruction Prefetching and Its Side Effects
Area 0
Area 1
Address
H'03FFFFF8
H'03FFFFFA
H'03FFFFFC
H'03FFFFFE
H'04000000
H'04000002
Figure F.1 Instruction Prefetch
ADD R1,R4
JMP @R2
NOP
NOP
.
.
.
.
.
F. Instruction Prefetching and Its Side Effects
Rev.4.00 Oct. 10, 2008 Page 1113 of 1122
Instruction prefetch address
PC (program counter)
REJ09B0370-0400