HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 223

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.5.3
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The entry to be accessed is specified in the address field, and the
write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the
entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry
specification. The address array bit [3] association bit (A bit) specifies whether or not association
is performed when writing to the OC address array. As only longword access is used, 0 should be
specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
The following three kinds of operation can be used on the OC address array:
1. OC address array read
2. OC address array write (non-associative)
3. OC address array write (associative)
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the UTLB. If the
addresses match and the V bit is 1, the U bit and V bit specified in the data field are written
into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no
operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit,
write-back is performed. If a UTLB miss occurs during address translation, or the comparison
shows a mismatch, an exception is not generated, no operation is performed, and the write is
OC Address Array
Rev.4.00 Oct. 10, 2008 Page 123 of 1122
REJ09B0370-0400
4. Caches