HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 695

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5,
DMA Operation Register (DMAOR).
Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME
bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is
enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are
suspended.
Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the
DME bit in section 14.2.5, DMA Operation Register (DMAOR).
14.8
Operation specific to the SH7751R is described here. For details of operation, see section 14.3,
Operation.
14.8.1
In normal DMA transfer mode, the DMAC always operates with eight channels, and external
requests are only accepted on channel 0 (DREQ0) and channel 1 (DREQ1).
After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR,
DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1,
DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends
when the transfer-end condition is satisfied. There are three modes for transfer requests: auto-
request, external request, and on-chip peripheral module request. The addressing modes for DMA
transfer are the single-address mode and the dual-address mode. Bus mode is selectable between
burst mode and cycle steal mode.
14.8.2
For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels.
External requests are accepted on channels 0−3 when DMAOR.DBL = 0, and on channels 0−7
when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in
section 14.7.5, DMA Operation Register (DMAOR).
Operation (SH7751R)
Channel Specification for a Normal DMA Transfer
Channel Specification for DDT-Mode DMA Transfer
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 595 of 1122
REJ09B0370-0400