UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 153
UPD78F9201MA-CAC-A
Manufacturer Part Number
UPD78F9201MA-CAC-A
Description
MCU 8BIT 2KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9500MA-CAC-A.pdf
(342 pages)
Specifications of UPD78F9201MA-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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8.4
8.4.1
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The operation clock of watchdog timer is fixed to low-speed internal oscillation clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
A status transition diagram is shown below
Operation of Watchdog Timer
The status after reset release is as follows.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by
option byte
Operation clock: Low-speed internal oscillation clock
Cycle: 2
Counting starts
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
2.
execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to
bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1, 2
18
/f
RL
.
(546.13 ms: At operation with f
CHAPTER 8 WATCHDOG TIMER
User’s Manual U18172EJ3V0UD
RL
= 480 kHz (MAX.))
151
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