UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 149
UPD78F9202MA-CAC-A
Manufacturer Part Number
UPD78F9202MA-CAC-A
Description
MCU 8BIT 4KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9500MA-CAC-A.pdf
(342 pages)
Specifications of UPD78F9202MA-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F9202MA-CAC-A
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset
Watchdog timer clock
source
Operation after reset
Operation mode
selection
Features
Remarks 1. f
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock
period).
source of the watchdog timer.
<1> If the clock source is f
<2> If the clock source is f
2. f
RL
X
When f
In HALT/STOP mode
During oscillation stabilization time
: System clock oscillation frequency
If the CPU clock is f
In HALT/STOP mode
: Low-speed internal oscillation clock oscillation frequency
Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode
Fixed to f
Operation starts with the maximum interval (2
The interval can be changed only once.
The watchdog timer cannot be stopped.
Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software
X
is stopped
RL
Note 1
.
X
RL
X
, clock supply to the watchdog timer is stopped under the following conditions.
and if f
, clock supply to the watchdog timer is stopped under the following conditions.
CHAPTER 8 WATCHDOG TIMER
User’s Manual U18172EJ3V0UD
RL
is stopped by software before execution of the STOP instruction
Option Byte Setting
18
/f
RL
). Operation starts with the maximum interval
(2
The clock selection/interval can be changed only
once.
The watchdog timer can be stopped
18
Selectable by software (f
When reset is released: f
/f
RL
).
X
RL
, f
RL
or stopped)
Note 2
.
147
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