UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 50
UPD78F9202MA-CAC-A
Manufacturer Part Number
UPD78F9202MA-CAC-A
Description
MCU 8BIT 4KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9500MA-CAC-A.pdf
(342 pages)
Specifications of UPD78F9202MA-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F9202MA-CAC-A
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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3.4.2 Short direct addressing
48
[Function]
[Description example]
[Illustration]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH
(internal high-speed RAM) + FF00H to FF1FH (special function registers)).
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,
and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 80H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
EQU DATA1 0FE90H ; DATA1 shows FE90H of a saddr area,
MOV DATA1, #50H
Effective
address
Identifier
saddrp
15
saddr
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
7
1
Instruction code
1
1
saddr-offset
OP code
Label or FE80H to FF1FH immediate data
Label or FE80H to FF1FH immediate data (even address only)
1
; When setting the immediate data to 50H
1
1
1
1
0
1
CHAPTER 3 CPU ARCHITECTURE
0
1
1
0
8
User’s Manual U18172EJ3V0UD
1
0
0
Description
1
1
1
= 1.
= 0.
0
0
0
1
0
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
Short direct memory
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