UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 569
UPD78F0552MA-FAA-AX
Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0552MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
15.6 Timing Charts
devices as its communication partner.
(IICAS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO latch and is output (MSB first) via the SDAA0 pin.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
When using the I
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0
Figures 15-33 and 15-34 show timing charts of the data communication.
The IICA shift register (IICA)’s shift operation is synchronized with the falling edge of the serial clock (SCLA0). The
Data input via the SDAA0 pin is captured into IICA at the rising edge of SCLA0.
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
CHAPTER 15 SERIAL INTERFACE IICA
555
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