UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 517
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
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Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF91H
(2) Serial status register 0 (CSIS0)
Notes 1.
Caution Be sure to clear bit 7 to 0.
Remark
Symbol
CSIS0
This is an 8-bit register used to select the base clock, control the communication operation, and indicate the
status of serial interface CSIA0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
prohibited when bit 0 (TSF0) is 1.
Reset signal generation clears this register to 00H.
2.
3.
4.
5.
6.
7.
f
PRS
Bits 0 and 1 are read-only.
Make sure that bit 7 (CSIAE0) of the Serial Operation Mode Specification Register 0 (CSIMA0) = 0 when
rewriting the CKS00 bit.
The frequency that can be used for the peripheral hardware clock (f
supply voltage and product specifications.
If the peripheral hardware clock (f
0), when 1.8 V ≤ V
This is settable only if 4.0 V ≤ V
STBE0 is valid only in master mode.
When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the
setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks are
used for 1-byte transfer if ADTI0 = 00H is set.
(The values shown in the table above are those when f
STBE0
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
(Standard products and
(A) grade products only)
: Peripheral hardware clock frequency
CKS00
After reset: 00H
0
1
0
1
7
0
Supply Voltage
Notes 6, 7
DD
DD
DD
≤ 5.5 V
< 4.0 V
< 2.7 V
Figure 17-3. Format of Serial Status Register 0 (CSIS0) (1/2)
Strobe output disabled
Strobe output enabled
CKS00
f
f
PRS
PRS
Note 4
/2
DD
6
Note 2
< 2.7 V, the setting of CKS00 = 0 (base clock: f
R/W
Note 1
STBE0
f
f
f
Conventional-specification Products
PRS
PRS
PRS
f
PRS
DD
5
(
μ
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz
2 MHz
1 MHz
= 2 MHz
PD78F05xx and 78F05xxD)
≤ 5.5 V.
PRS
) operates on the internal high-speed oscillation clock (f
BUSYE0
4
Base clock (f
Strobe output enable/disable
f
PRS
2.5 MHz
5 MHz
BUSYLV0
= 5 MHz
PRS
CHAPTER 17 SERIAL INTERFACE CSIA0
W
3
) selection
= f
XH
(XSEL = 1).)
f
f
Note 3
PRS
PRS
ERRE0
f
PRS
PRS
Expanded-specification Products
(
μ
PRS
2
PD78F05xxA and 78F05xxDA)
10 MHz
≤ 20 MHz
≤ 5 MHz
5 MHz
= 10 MHz
) is prohibited.
) differs depending on the power
However, rewriting CSIS0 is
ERRF0
1
f
PRS
20 MHz
10 MHz
= 20 MHz
TSF0
RH
Note 5
0
) (XSEL =
517
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