UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 718
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
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Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
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Quantity:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: 0080H/1080H
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited.
Remarks 1.
swap operation.
2.
2. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V ≤ V
3. The watchdog timer continues its operation during self-programming and EEPROM emulation of
4. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
5. Be sure to clear bit 7 to 0.
WINDOW1
LSROSC
WDTON
WDCS2
2.7 V.
the flash memory.
overflow time and window size taking this delay into consideration.
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the
internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
f
( ): f
RL
7
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
: Internal low-speed oscillation clock frequency
RL
Note
= 264 kHz (MAX.)
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
WINDOW1
WINDOW0
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
Figure 26-1. Format of Option Byte (1/2)
25%
50%
75%
100%
WINDOW0
During processing, the interrupt acknowledge time is delayed.
Operation control of watchdog timer counter/illegal access detection
WDCS0
5
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
Internal low-speed oscillator operation
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
4
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
WDCS1
2
CHAPTER 26 OPTION BYTE
WDCS0
1
LSROSC
0
Set the
DD
718
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