UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 296
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4.3 Setting window open period of watchdog timer
byte (000C0H). The outline of the window is as follows.
294
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
Example: If the window open period is 25%
Caution When data is written to WDTE for the first time after reset release, the watchdog timer is cleared
The window open period to be set is as follows.
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory
Counting
starts
again.
reset signal is generated.
in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
WINDOW1
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
3. Do not set the window open period to 25% if the watchdog timer corresponds to either of the
and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.
regardless of the values of WINDOW1 and WINDOW0.
conditions below.
0
0
1
1
Internal reset signal is generated
if “ACH” is written to WDTE.
• When used at a supply voltage (V
• When stopping all main system clocks (internal high-speed oscillation clock, X1 clock,
• Low-power consumption mode
Window close period (75%)
and external main system clock) by use of the STOP mode or software.
Table 8-4. Setting Window Open Period of Watchdog Timer
WINDOW0
0
1
0
1
25%
50%
75%
100%
CHAPTER 8 WATCHDOG TIMER
User’s Manual U17854EJ9V0UD
Window Open Period of Watchdog Timer
DD
) below 2.7 V.
Counting starts again when
“ACH” is written to WDTE.
Window open
period (25%)
Overflow
time
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