UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 843
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3-wire
serial
(CSI00,
CSI10,)
communic
ation
UART
(UART0,
UART1,
UART3)
communic
ation
Function
I/O
Master
Reception
(in
Reception
Mode)
Master
transmission/
reception
Master
transmission/
reception (in
continuous
transmission/
reception mode)
Slave
transmission
Slave transmission
(in continuous
transmission mode)
Slave reception
Slave
transmission/
reception
Slave
transmission/
reception (in
continuous
transmission/
reception mode)
UART
transmission
UART
transmission (in
continuous
transmission
mode)
UART reception
Calculating baud
rate
Details of
Function
Continuous
−
The MD0n0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
The MD0n0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
The MDmn0 bit can be rewritten even during operation.
The MD0n0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last receive data.
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
The MD0n0 bit can be rewritten even during operation. However, rewrite it before
transfer of the last bit is started.
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
Be sure to set transmit data to the SlOp register before the clock from the master is
started.
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
When using serial array units 0 and 1 as UARTs, the channels of both the
transmitting side (even-number channel) and the receiving side (odd-number
channel) can be used only as UARTs.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
For the UART reception, be sure to set SMRmr of channel r that is to be paired with
channel n.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
389, 391
398, 400
409, 411,
413, 415
413, 415
427, 429
p.382
pp.386,
p.390
pp.394,
p.399
pp.403,
406
pp.408,
pp.409,
p.414
p.419
pp.423,
p.428
pp.431,
432
pp.433,
436
p.445
841
(17/33)
Page
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