UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 549
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.2 Configuration of Multiplier
MULOH
MULOL
Symbol
Symbol
Symbol
Symbol
MULA
MULB
Figure 13-2. Format of 16-bit higher multiplication result storage register and 16-bit lower multiplication
(1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage
(2) Multiplication input data registers A, B (MULA, MULB)
register (MULOH, MULOL)
These two registers, MULOH and MULOL, are used to store a 32-bit multiplication result. The higher 16 bits
of the multiplication result are stored in MULOH and the lower 16 bits, in MULOL, so that a total of 32 bits of
the multiplication result can be stored.
These registers hold the result of multiplication after the lapse of one CPU clock.
MULOH and MULOL can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
These are 16-bit registers that store data for multiplication. The multiplier multiplies the values of MULA and
MULB.
MULA and MULB can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
Address: FFFF0H, FFFF1H
Address: FFFF2H, FFFF3H
Address: FFFF4H, FFFF5H
Address: FFFF6H, FFFF7H
Figure 13-3. Format of Multiplication input data registers A, B (MULA, MULB)
FFFF1H
FFFF3H
FFFF5H
FFFF7H
result storage register (MULOH, MULOL)
After reset: 0000H
After reset: 0000H
After reset: 0000H
After reset: 0000H
CHAPTER 13 MULTIPLIER
User’s Manual U17854EJ9V0UD
R/W
R/W
R
R
FFFF0H
FFFF2H
FFFF4H
FFFF6H
547
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