UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 576
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD78F1144AGK-GAJ-AX
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(2) DMA response time
(3) Operation in standby mode
The response time of DMA transfer is as follows.
The DMA controller operates as follows in the standby mode.
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
HALT mode
STOP mode
Remark 1 clock: 1/f
Response time
Status
2. When executing a DMA pending instruction (see 14.6 (4)), the maximum response
3. Do not specify successive transfer triggers for a channel within a period equal to the
time is extended by the execution time of that instruction to be held pending.
maximum response time plus one clock cycle, because they might be ignored.
transfer.
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
CLK
Table 14-3. DMA Operation in Standby Mode
Table 14-2. Response Time of DMA Transfer
(f
CLK
CHAPTER 14 DMA CONTROLLER
: CPU clock)
User’s Manual U17854EJ9V0UD
3 clocks
Minimum Time
DMA Operation
10 clocks
Maximum Time
Note
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