UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 580
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
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578
Maskable
Software
Reset
Interrupt
Type
Notes 1.
2.
3.
4.
Priority
Default
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 37 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
−
−
Note 1
INTAD
INTRTC
INTRTCI
INTKR
INTTM04
INTTM05
INTTM06
INTTM07
INTP6
INTP7
INTP8
INTP9
INTP10
INTP11
BRK
RESET
POC
LVI
WDT
TRAP
Name
End of A/D conversion
Fixed-cycle signal of real-time counter/alarm
match detection
Key return signal detection
End of timer channel 4 count or capture
End of timer channel 5 count or capture
End of timer channel 6 count or capture
End of timer channel 7 count or capture
Pin input edge detection
Execution of BRK instruction
RESET pin input
Power-on-clear
Low-voltage detection
Overflow of watchdog timer
Execution of illegal instruction
Interval signal detection of real-time counter
Table 15-1. Interrupt Source List (2/2)
CHAPTER 15 INTERRUPT FUNCTIONS
Interrupt Source
User’s Manual U17854EJ9V0UD
Trigger
Note 3
Note 4
Internal
External
Internal
External
Internal/
External
−
−
Address
004CH
003AH
004AH
004EH
007EH
Vector
0034H
0036H
0038H
0042H
0044H
0046H
0048H
0050H
0052H
0054H
0000H
Table
Configuration
Type
Basic
(C)
(D)
(A)
(A)
(B)
−
Note 2
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