UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 428
UPD78F0386GK-8EU-A
Manufacturer Part Number
UPD78F0386GK-8EU-A
Description
MCU 96KB FLASH 5KB RAM
Manufacturer
Renesas Electronics America
Series
78K0/Lx2r
Datasheet
1.UPD78F0372GK-8EU-A.pdf
(624 pages)
Specifications of UPD78F0386GK-8EU-A
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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(3) Operation
<1> The start condition is transmitted.
<2> The slave ID is transmitted (first time) (from the 1st to 7th clocks).
<3> R/W information (0) is transmitted (at the 8th clock).
<4> An acknowledge signal is received (at the rising edge of the 9th clock).
<5> The read start address is transmitted (from the 1st to 8th clocks following <4>).
<6> An acknowledge signal is received (at the rising edge of the 9th clock).
<7> The restart condition is transmitted.
<8> The slave ID is transmitted (second time) (from the 1st to 7th clocks following <7>).
<9> R/W information (1) is transmitted (at the 8th clock).
<10> An acknowledge signal is received (at the rising edge of the 9th clock).
<11> Read data is received (first time) (from the 1st to 8th clocks following <10>).
<13> Read data is received (second time) (from the 1st to 8th clocks following <12>).
<14> Stop the acknowledge signal transmission.
<15> The stop condition is transmitted.
Note
<12> An acknowledge signal is transmitted (from the falling edge of the 8th clock to the falling edge of the 9th
The operation flow when receiving read data twice is shown below.
Steps <1> to <15> correspond to <1> to <15> in Figure 16-34.
clock).
(The address is automatically incremented by 1.)
Do not transmit the acknowledge signal when completing data reception.
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
Note
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