UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 452
UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 452 of 880
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<R>
11.7 Operation of Simplified I
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices
such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master and does not
have a wait detection function. Make sure by using software, as well as operating the control registers, that the AC
specifications of the start and stop conditions are observed.
450
0
1
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
[Data transmission/reception]
[Interrupt function]
[Error detection flag]
* [Functions not supported by simplified I
Note An ACK is not output when the last data is being received by writing 0 to the SOE02 (SOE0 register) bit and
Remark To use an I
The channels supporting simplified I
Simplified I
Unit
• Address field transmission
• Data transmission
• Data reception
• Stop condition generation
• Master transmission, master reception (only master function with a single master)
• ACK output function
• Data length of 8 bits
• Manual generation of start condition and stop condition
• Transfer end interrupt
• Overrun error
• Parity error (ACK error)
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection function
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
stopping the output of serial communication data. See 11.7.3 (2) Processing flow for details.
2
C (IIC10) performs the following four types of communication operations.
0
1
2
3
0
1
2
3
Channel
2
C bus of full function, see CHAPTER 12 SERIAL INTERFACE IIC0.
Note
and ACK detection function
2
C (IIC10) Communication
Used as CSI
(See 11.7.1.)
(See 11.7.2.)
(See 11.7.3.)
(See 11.7.4.)
2
C (IIC10) are channel 2 of SAU0.
CSI00
CSI10
CHAPTER 11 SERIAL ARRAY UNIT
−
−
−
−
−
−
2
C]
User’s Manual U17854EJ9V0UD
UART3 (supporting LIN-bus)
Used as UART
UART1
UART0
−
−
Used as Simplified I
IIC10
−
−
−
−
−
−
−
2
C
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