UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 799
UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1. Lower default priority
Caution To service multiple interrupts, the values of the EIPC and EIPSW registers must be saved
Interrupt request o
Interrupt request s
Interrupt request i
Interrupt request l
2. Higher default priority
Figure 21-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
before executing the EI instruction. When returning from multiple interrupt servicing, restore
the values of EIPC and EIPSW after executing the DI instruction.
(level 2)
(level 2)
(level 3)
(level 1)
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Main routine
EI
Interrupt request n
request p
Interrupt request u
Interrupt
(level 2)
Interrupt request k
Interrupt
request j
(level 3)
(level 1)
(level 3)
(level 1)
request m
(level 2)
(level 2)
While an Interrupt Is Being Serviced (2/2)
request t
Interrupt
Interrupt
EI
Servicing of o
EI
request q
Interrupt
(level 1)
Servicing of i
Servicing of j
Servicing of s
Note 1
Servicing of l
Servicing of n
Note 2
Servicing of u
Servicing of t
Servicing of m
User’s Manual U18953EJ5V0UD
EI
Servicing of p
request r
Interrupt
(level 0)
Servicing of k
EI
Servicing of q
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
If levels 3 to 0 are acknowledged
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of r
797
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