UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 658
UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
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656
Maskable
Interrupt
Type
Notes 1.
2.
3.
4.
Priority
Default
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 44 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
Note 1
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTSR3
INTSRE3
INTDMA0
INTDMA1
INTST0
/INTCSI00
INTSR0
/INTCSI01
INTSRE0
INTST1
/INTCSI10
/INTIIC10
INTSR1
/INTCSI11
/INTIIC11
INTSRE1
INTIIC0
INTTM00
INTTM01
Name
Watchdog timer interval
(75% of overflow time)
Low-voltage detection
Pin input edge detection
UART3 transmission transfer end or buffer
empty interrupt
UART3 reception transfer end
UART3 reception communication error
occurrence
End of DMA0 transfer
End of DMA1 transfer
UART0 transmission transfer end or buffer
empty interrupt/CSI00 transfer end or buffer
empty interrupt
UART0 reception transfer end/
CSI01 transfer end or buffer empty interrupt
UART0 reception communication error
occurrence
UART1 transmission transfer end or buffer
empty interrupt/
CSI10 transfer end or buffer empty interrupt/
IIC10 transfer end
UART1 reception transfer end /CSI11 transfer
end or buffer empty interrupt/IIC11 transfer
end
End of IIC0 communication
End of timer array unit 0 channel 0 count or
capture
End of timer array unit 0 channel 1 count or
capture
UART1 reception communication error
occurrence
Table 17-1. Interrupt Source List (1/3)
CHAPTER 17 INTERRUPT FUNCTIONS
Interrupt Source
User’s Manual U18432EJ5V0UD
Trigger
Note 4
Note 3
Internal
External
Internal
Internal/
External
Address
000AH
000CH
000EH
001AH
001CH
001EH
002AH
002CH
002EH
Vector
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
0026H
0028H
Table
Configuration
Type
Basic
(A)
(B)
(A)
Note 2
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