UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 312

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4 Interrupt Requests
310
The following three types of interrupt requests are generated from UARTn.
The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt,
reception completion interrupt, and transmission completion interrupt.
(1) Reception error interrupt (INTSREn)
(2) Reception completion interrupt (INTSRn)
(3) Transmission completion interrupt (INTSTn)
• Reception error interrupt (INTSREn)
• Reception completion interrupt (INTSRn)
• Transmission completion interrupt (INTSTn)
When reception is enabled, a reception error interrupt is generated according to the logical OR of the three
types of reception errors explained for the ASISn register. Whether a reception error interrupt (INTSREn) or a
reception completion interrupt (INTSRn) is generated when an error occurs can be specified using the ISRMn
bit of the ASIMn register.
When reception is disabled, no reception error interrupt is generated.
When reception is enabled, a reception completion interrupt is generated when data is shifted in to the receive
shift register and transferred to the receive buffer register (RXBn).
A reception completion interrupt request can be specified to be generated in place of a reception error interrupt
using the ISRMn bit of the ASIMn register even when a reception error has occurred.
When reception is disabled, no reception completion interrupt is generated.
A transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit
characters is shifted out from the transmit shift register.
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
Table 13-1. Generated Interrupts and Default Priorities
Reception error
Reception completion
Transmission completion
User’s Manual U15905EJ2V1UD
Interrupt
Priority
1
2
3