UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 362
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Remark
Condition for clearing (SPD = 0)
• At the rising edge of the address transfer byte’s
• When IICE changes from 1 to 0
• After reset
Condition for clearing (ACKD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• After reset
Condition for clearing (STD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• After reset
ACKD
STD
SPD
first clock following setting of this bit and detection
of a start condition
following address transfer
LREL: Bit 6 of IIC control register (IICC)
IICE:
0
1
0
1
0
1
ACK was not detected.
ACK was detected.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect
Bit 7 of IIC control register (IICC)
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Detection of start condition
Detection of stop condition
Detection of ACK
Condition for setting (SPD = 1)
When a stop condition is detected
Condition for setting (STD = 1)
Condition for setting (ACKD = 1)
• After the SDA line is set to low level at the rising
When a start condition is detected
edge of the SCL’s ninth clock
2
C BUS
(3/3)
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