UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 403
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
UPD70F3201YGC-YEU-A
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15.16 Timing of Data Communication
devices as its communication partner.
which specifies the data transfer direction and then starts serial communication with the slave device.
The transmit data is transferred to the SO latch and is output (MSB first) via the SDA pin.
When using I
After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IIC status register (IICS)),
The shift operation of the IIC bus shift register (IIC) is synchronized with the falling edge of the serial clock (SCL).
Data input via the SDA pin is captured by IIC at the rising edge of SCL.
The data communication timing is shown below.
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
2
C BUS
401
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