UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 46
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(10) PCS0 to PSC3 (Port CS) (V850ES/SA2) … 3-state I/O
[V850ES/SA2]
Port CS is a 4-bit I/O port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PCS0 to PSC3 also operate as the control signal
output pins when the memory and peripheral I/O are expanded externally.
(a) Port mode
(b) Control mode
[V850ES/SA3]
Port CS is an 8-bit I/O port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PCS0 to PSC3 also operate as the control signal
output pins when the memory and peripheral I/O are expanded externally.
(a) Port mode
(b) Control mode
PCS0 to PCS5 (Port CS) (V850ES/SA3) … 3-state I/O
PCS0 to PSC3 can be set to the input or output mode in 1-bit units by using port mode register CM
(PMCS).
(i) CS0 to CS3 (chip select) … Output
PCS0 to PCS7 can be set to the input or output mode in 1-bit units by using port mode register CS
(PMCS).
(i) CS0 to CS3 (chip select) … Output
These are the chip select signals for the SRAM, external ROM, and external peripheral I/O area.
The CSn signal is assigned to memory block n (n = 0 to 3).
Each of these signals is active while the bus cycle accessing the corresponding memory block is being
executed, and inactive in the idle state (TI).
These are the chip select signals for the SRAM, external ROM, and external peripheral I/O area.
The CSn signal is assigned to memory block n (n = 0 to 3).
Each of these signals is active while the bus cycle accessing the corresponding memory block is being
executed, and inactive in the idle state (TI).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15905EJ2V1UD
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