UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 212
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 212 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
4.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn)
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
Explanation:
P11 to P17
Port 1 output latch
0
P10
0
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0R/Lx3 Microcontrollers.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
0
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
0
•
•
in 8-bit units.
Pin status: High-level
Low-level output
0
In the case of P10, an output port, the value of the port output latch (0) is read.
In the case of P11 to P17, input ports, the pin status (1) is read.
0
Figure 4-52. Bit Manipulation Instruction (P10)
0
0
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P11 to P17
Port 1 output latch
1
P10
1
CHAPTER 4 PORT FUNCTIONS
1
1
Pin status: High-level
High-level output
1
1
1
1
212
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