UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 556
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 556 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0, UART1, UART2, UART3) communication can
be calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
As shown in Figure 14-87, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of the serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
(Maximum receivable baud rate) =
(Minimum receivable baud rate) =
Brate: Calculated baud rate value at the reception side (See 14.6.5 (1) Baud rate calculation expression.)
k:
Nfr:
Permissible maximum
Permissible minimum
Data frame length
Figure 14-87. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
data frame length
data frame length
SDRmn[15:9] + 1
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
of SAU
timing
Latch
Start
Start
bit
Start
bit
bit
2 × k × Nfr − k + 2
2 × k × Nfr − k − 2
Bit 0
2 × k × (Nfr − 1)
Bit 0
FL
Bit 0
2 × k × Nfr
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
(11 × FL) min.
(11 × FL) max.
× Brate
× Brate
Bit 7
CHAPTER 14 SERIAL ARRAY UNIT
Bit 7
Bit 7
Parity
bit
Parity
bit
Parity
bit
Stop
bit
Stop
bit
Stop
bit
556
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