UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 576
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0R/Lx3
14.9 Relationship Between Register Settings and Pins
and 1.
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Note1
Remarks 1. X: Don’t care
SE
00
0
1
Table 14-5. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, UART0 transmission)
Tables 14-5 to 14-12 show the relationship between register settings and pins for each channel of serial array units 0
MD
002
0
0
0
0
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin (refer to Table 14-6).
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART0 transmission and reception in a pair, set channel 1 of unit 0 to UART0 reception (refer to
001
MD
In this case, operation stop mode or UART0 transmission must be selected for channel 0 of unit 0.
m (SOm).
Table 14-6).
0
1
0
1
2. For 78K0R/LF3, the channel 0 of unit 0 is not mounted.
SOE
00
0
0
1
1
0
1
1
1
Note4
Note4
Note4
Note4
Note4
0/1
0/1
SO
0/1
0/1
0/1
00
1
1
1
CKO
Note4
Note4
Note4
0/1
0/1
0/1
00
1
1
1
1
1
TXE
00
0
0
1
1
0
1
1
1
RXE
00
0
1
0
1
1
0
1
0
Note3
Note3
PM
80
×
1
1
1
0
0
0
×
Note3
Note3
P80 PM
×
×
×
×
1
1
1
×
Note2
Note3
Note3
Note3
Note3
81
×
1
×
1
1
×
1
×
Note3
Note3
Note2
Note3
Note3
P81
×
×
×
×
×
×
×
×
Note3
Note3
Note3
PM
82
×
0
0
×
0
0
0
×
Note3
Note3
P82
Note3
×
×
×
1
1
1
1
1
transmission
Operation mode
Operation stop
Master CSI00
Master CSI00
Master CSI00
transmission/
transmission/
transmission
transmission
Slave CSI00
Slave CSI00
Slave CSI00
reception
reception
reception
reception
UART0
mode
CHAPTER 14 SERIAL ARRAY UNIT
Note5
INTP11/
INTP11/
(output)
(output)
(output)
SCK00/
INTP11
SCK00
SCK00
SCK00
SCK00
SCK00
SCK00
(input)
(input)
(input)
/P80
P80
P80
SI00/RxD0/
INTP9/P81
INTP9/P81
INTP9/P81
INTP9/P81
INTP9/P81
Pin Function
P81
INTP9/
RxD0/
RxD0/
SI00
SI00
SI00
SI00
Note2
TxD0/P82
SO00/
SO00
SO00
SO00
SO00
TxD0
P82
P82
P82
576
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