UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 735
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 735 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
transmitted data is written using software in this example. The data of the second and following bytes is automatically
transmitted.
to be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.)
(INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA transfer, the CSI
transfer must be completed.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
INTDMA0
During CSI transfers, no CSI interrupt is generated when the transmitted data of the first byte is written. Therefore, the
The received data is automatically transferred from the first byte. (In successive transmission/reception, the data that is
A DMA interrupt (INTDMA1) occurs when the last transmit data has been writing to the data register. A DMA interrupt
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7
Forcible termination by software).
occurs.
DST0 = 0
DEN0 = 0
RETI
Note
Setting for CSI transfer
SIO00 (= SDR00 [7:0])
Write transmit data to
Figure 18-9. Setting Example of CSI Transmission/reception
DBC1 = 00FFH
DRA0 = F100H
DBC0 = 0100H
DRA1 = F201H
User program
DMC0 = 06H
DMC1 = 46H
DSA0 = 10H
DSA1 = 10H
processing
DEN0 = 1
DEN1 = 1
DST0 = 1
DST1 = 1
Start
End
DST1 = 0
DEN1 = 0
RETI
INTCSI00 occurs.
INTDMA1
Note
occurs.
DMA0 transfer CSI reception
DMA1 transfer CSI transmission
CHAPTER 18 DMA CONTROLLER
Hardware operation
735
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