UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 210
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 210 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(3) TMPn I/O control register 0 (TPnIOC0)
The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnIOC0
After reset: 00H
Note The output level of the timer output pin (TOPnm) specified by the
Cautions 1. Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits
TPnOE1
TPnOE0
TPnOL1
TPnOL0
0
1
0
1
0
1
0
1
7
0
• When TPnOLm bit = 0
TPnOLm bit is shown below (m = 0, 1).
TOPnm output pin
Timer output disabled
• When TPnOL1 bit = 0: Low level is output from the TOPn1 pin
• When TPnOL1 bit = 1: High level is output from the TOPn1 pin
Timer output disabled
• When TPnOL0 bit = 0: Low level is output from the TOPn0 pin
• When TPnOL0 bit = 1: High level is output from the TOPn0 pin
Timer output enabled (a square wave is output from the TOPn1 pin).
Timer output enabled (a square wave is output from the TOPn0 pin).
R/W
2. Even if the TPnOLm bit is manipulated when the TPnCE
TOPn1 pin output starts at high level
TOPn1 pin output starts at low level
TOPn0 pin output starts at high level
TOPn0 pin output starts at low level
16-bit counter
6
0
when the TPnCTL0.TPnCE bit = 0. (The same value can be
written when the TPnCE bit = 1.)
mistakenly performed, clear the TPnCE bit to 0 and then
set the bits again.
and TPnOEm bits are 0, the TOPnm pin output level varies
(m = 0, 1).
TPnCE bit
Address: TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H,
5
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TOPn1 pin output level setting
TOPn0 pin output level setting
TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H,
TP4IOC0 FFFFF5D2H, TP5IOC0 FFFFF5E2H
TOPn1 pin output setting
TOPn0 pin output setting
4
0
TPnOL1 TPnOE1 TPnOL0
• When TPnOLm bit = 1
3
TOPnm output pin
16-bit counter
TPnCE bit
<2>
Note
Note
If rewriting was
1
TPnOE0
<0>
Page 194 of 870
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