UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 243
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 243 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
<1> Count operation start flow
<2> TPnCCR0 and TPnCCR1 register
setting change flow
(TPnCKS0 to TPnCKS2 bits)
Setting of TPnCCR0 register
Setting of TPnCCR1 register
Register initial setting
TPnCCR0 register,
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
Remark
TPnCCR1 register
TPnCTL0 register
TPnCE bit = 1
START
Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
n = 0 to 5
m = 0, 1
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
Trigger wait status
TPnCCR1 register write
processing is necessary
only when the set
cycle is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
<3> TPnCCR0, TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
<5> Count operation stop flow
setting change flow
setting change flow
Setting of TPnCCR1 register
Setting of TPnCCR0 register
Setting of TPnCCR1 register
TPnCE bit = 0
STOP
Counting is stopped.
Only writing of the TPnCCR1
register must be performed when
When the counter is cleared after
setting, the value of the
TPnCCRm register is transferred
to the CCRm buffer register.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
the set duty factor is changed.
Page 227 of 870
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