UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 556
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
(12) Start condition generator
(13) Stop condition generator
(14) Bus status detector
This circuit controls the generation of interrupt request signals (INTIICn).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit)
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock (n = 0 to 2).
This circuit controls the wait timing.
These circuits are used to generate and detect various statuses.
This circuit generates the hold time for data corresponding to the falling edge of the SCL0n pin.
A start condition is generated when the IICCn.STTn bit is set.
However, in the communication reservation disabled status (IICFn.IICRSVn bit = 1), this request is ignored and the
IICFn.STCFn bit is set to 1 if the bus is not released (IICFn.IICBSYn bit = 1).
A stop condition is generated when the IICCn.SPTn bit is set.
Whether the bus is released or not is ascertained by detecting a start condition and stop condition.
However, the bus status cannot be detected immediately after operation, so set the bus status detector to the
initial status by using the IICFn.STCENn bit.
Remark
2
C interrupt is generated following either of two triggers.
n = 0 to 2
CHAPTER 17 I
Page 540 of 870
2
C BUS
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