UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 561
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 561 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Note Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0, the SPTn bit must be set
Caution When the TRCn bit = 1, the WRELn bit is set to 1 during the ninth clock and the wait state
Remarks 1. The SPTn bit is 0 if it is read immediately after data setting.
Cautions concerning set timing
For master reception:
For master transmission: A stop condition cannot be generated normally during the ACK reception period. Set to
• Cannot be set to 1 at the same time as the STTn bit.
• The SPTn bit can be set to 1 only when in master mode
• When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of
• When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPTn bit = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• When the LRELn bit = 1 (communication save)
• When the IICEn bit = 0 (operation stop)
• After reset
SPTn
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPTn bit should be set to 1 during the wait period that follows output of the ninth clock.
0
1
to 1 and a stop condition generated before the first stop condition is detected following the switch to the
operation enabled status. For details, see 17.15 Cautions.
is canceled, after which the TRCn bit is cleared to 0 and the SDA0n line is set to high
impedance.
2. n = 0 to 2
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n
pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed
from low level to high level and a stop condition is generated.
Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period
after the slave has been notified of final reception.
1 during the wait period that follows output of the ninth clock.
Cannot be set to 1 during transfer.
Stop condition trigger
Note
Condition for setting (SPTn bit = 1)
• Set by instruction
.
CHAPTER 17 I
Page 545 of 870
2
C BUS
(4/4)
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