UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1129
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) UF0 EP0 length register (UF0E0L)
UF0E0L
The UF0E0L register stores the data length held by the UF0E0R register.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is
abnormal reception, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The interrupt
request is generated only when the reception is normal, and the FW can read as many data from the UF0E0R
register as the value read from the UF0E0L register. The value of the UF0E0L register is decremented each time
the UF0E0R register has been read.
Bit position
Status of UF0E0R
UF0EPS0
7 to 0
UF0E0N register
UF0IS1
EP0NKR bit of
E0ODT
EP0R
E0L7
7
register
register
register
E0L7 to E0L0
bit of
bit of
Bit name
E0L6
6
E0L5
These bits store the data length held by the UF0E0R register.
5
Figure 21-4. Operation of UF0E0R Register
of reception
completion
Normal
E0L4
Reading
4
starts
FIFO
E0L3
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
completed
Reading
FIFO
E0L2
2
Hardware clear
Hardware clear
Hardware clear
Function
E0L1
1
Abnormal
reception
E0L0
0
FIFO
hard-
ware
clear
00200102H
Address
of reception
completion
Normal
Page 1129 of 1509
After reset
00H
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