UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1272
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
23.3 Maskable Interrupts
V850ES/JH3-H have 84 to 91 maskable interrupt sources.
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control
registers (programmable priority control).
signals is disabled and the interrupt disabled (DI) status is set.
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same
priority level cannot be nested.
executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of
EIPC and EIPSW.
23.3.1 Operation
another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this
case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt
request signal if either the maskable interrupt is unmasked or the NP and ID bits are set to 0 by using the RETI or LDSR
instruction.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Maskable interrupt request signals can be masked by interrupt control registers.
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while
How maskable interrupts are serviced is illustrated below.
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
The V850ES/JG3-H and
Page 1272 of 1509
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