UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 551
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin)
Clearing Method
Figure 9-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and
Encoder clear input
(TENC00 pin input)
(TENC01 pin input)
Table 9-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits
(TECR0 pin input)
The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by
the TT0IOC3.TT0SCE bit.
TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits.
The counter can be cleared by the methods described below only in the encoder compare mode.
(a) Clearing method <1>: By detecting edge of encoder clear signal (TECR0 pin) (TT0SCE bit = 0)
TT0CNT register
Peripheral clock
<1>
<2>
Encoder input
Encoder input
timing signal
When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral clock if
the valid edge of the TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected. At this time, an
encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the settings of the
TT0ZCL, TT0BCL, and TT0ACL bits is invalid.
INTTT0EC
interrupt
Count
TT0SCE Bit
0
1
N
The TT0SCE bit also controls, depending on its setting, the TT0IOC3.TT0ZCL,
TT0ZCL Bit
Invalid
Valid
N + 1
Counter clear
TT0UDS0 Bits = 11)
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
0000H
TT0BCL Bit
Invalid
Valid
0001H
TT0ACL Bit
Invalid
Valid
TT0ECS1, TT0ECS0 Bits
0002H
Invalid
Valid
Page 551 of 1509
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