UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 14
UPD70F3744GJ-GAE-AX
Manufacturer Part Number
UPD70F3744GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3744GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3744GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 689
CHAPTER 21 STANDBY FUNCTION .................................................................................................. 691
CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 711
19.4
19.5
19.6
19.7
19.8
19.9
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
22.1
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
Software Exception .............................................................................................................. 674
19.4.1
19.4.2
19.4.3
Exception Trap...................................................................................................................... 677
19.5.1
19.5.2
External Interrupt Request Input Pins (NMI and INTP0 to INTP8) ................................... 681
19.6.1
19.6.2
Interrupt Acknowledge Time of CPU .................................................................................. 687
Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 688
Cautions ................................................................................................................................ 688
Function................................................................................................................................. 689
Register ................................................................................................................................. 690
Cautions ................................................................................................................................ 690
Overview................................................................................................................................ 691
Registers ............................................................................................................................... 693
HALT Mode............................................................................................................................ 696
21.3.1
21.3.2
IDLE1 Mode ........................................................................................................................... 698
21.4.1
21.4.2
IDLE2 Mode ........................................................................................................................... 700
21.5.1
21.5.2
21.5.3
STOP Mode............................................................................................................................ 703
21.6.1
21.6.2
21.6.3
Subclock Operation Mode ................................................................................................... 707
21.7.1
21.7.2
Sub-IDLE Mode ..................................................................................................................... 709
21.8.1
21.8.2
Overview................................................................................................................................ 711
Priorities of maskable interrupts...............................................................................................664
Interrupt control register (xxICn) ..............................................................................................668
Interrupt mask registers 0 to 4 (IMR0 to IMR4) ........................................................................670
In-service priority register (ISPR) .............................................................................................672
ID flag ......................................................................................................................................673
Watchdog timer mode register 2 (WDTM2) .............................................................................673
Operation .................................................................................................................................674
Restore ....................................................................................................................................675
EP flag .....................................................................................................................................676
Illegal opcode definition............................................................................................................677
Debug trap ...............................................................................................................................679
Noise elimination......................................................................................................................681
Edge detection .........................................................................................................................681
Setting and operation status ....................................................................................................696
Releasing HALT mode.............................................................................................................696
Setting and operation status ....................................................................................................698
Releasing IDLE1 mode ............................................................................................................698
Setting and operation status ....................................................................................................700
Releasing IDLE2 mode ............................................................................................................700
Securing setup time when releasing IDLE2 mode ...................................................................702
Setting and operation status ....................................................................................................703
Releasing STOP mode ............................................................................................................703
Securing oscillation stabilization time when releasing STOP mode .........................................706
Setting and operation status ....................................................................................................707
Releasing subclock operation mode ........................................................................................707
Setting and operation status ....................................................................................................709
Releasing sub-IDLE mode .......................................................................................................709
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