UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 340
UPD70F3744GJ-GAE-AX
Manufacturer Part Number
UPD70F3744GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3744GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3744GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JJ3
each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is
transferred to the CCR0 buffer register.
to 0000H, and a compare match interrupt request signal (INTTQ0CC0) is generated.
value of TQ0CCR0 register + 1) times.
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The INTTQ0CC0 signal is generated each time the valid edge of the external event count input has been detected (set
TQ0IOC0
TQ0IOC2
TQ0CTL0
TQ0CTL1
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
(c) TMQ0 I/O control register 0 (TQ0IOC0)
(d) TMQ0 I/O control register 2 (TQ0IOC2)
(e) TMQ0 counter read buffer register (TQ0CNT)
The count value of the 16-bit counter can be read by reading the TQ0CNT register.
TQ0OL3
TQ0CE
0/1
0
0
0
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
TQ0OE3 TQ0OL2 TQ0OE2
TQ0EST
0
0
0
0
TQ0EEE
0
0
0
0
0
0
0
0
TQ0EES1
TQ0OL1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0/1
0
0
0
TQ0EES0 TQ0ETS1 TQ0ETS0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0OE1 TQ0OL0 TQ0OE0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
0
0
0
0
0
0
0
0
0
0
1
0: Disable TOQ00 pin output
0: Disable TOQ01 pin output
Select valid edge
of external event
count input
0: Disable TOQ02 pin output
0: Disable TOQ03 pin output
0: Stop counting
1: Enable counting
0, 0, 1:
External event count mode
Page 324 of 892
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