UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 508
UPD70F3744GJ-GAE-AX
Manufacturer Part Number
UPD70F3744GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3744GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3744GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JJ3
15.7 Dedicated Baud Rate Generator
generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Note Only UARTA0 is valid; setting UARTA1 to UARTA3 is prohibited.
Remarks 1. n = 0 to 3
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0
bits is supplied to the 8-bit counter. This clock is called the base clock (f
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 3).
The base clock is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
ASCKA0
f
XX
f
f
f
XX
XX
XX
2. f
f
f
f
/1024
XX
XX
XX
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
Note
f
f
XX
/2
/4
/8
XX
UCLK
: Main clock frequency
: Base clock frequency
UAnCKS3 to UAnCKS0
UAnCTL1:
Figure 15-16. Configuration of Baud Rate Generator
UAnPWR
Selector
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
f
UCLK
UAnPWR, UAnTXEn bits
UAnBRS7 to UAnBRS0
Match detector
8-bit counter
UAnCTL2:
(or UAnRXE bit)
UCLK
1/2
).
Baud rate
Page 492 of 892
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