UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 736
UPD70F3744GJ-GAE-AX
Manufacturer Part Number
UPD70F3744GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3744GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3744GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JJ3
23.1 Functions
when oscillation of the main clock is stopped.
means other than reset.
Registers to Check Reset Source.
23.2 Configuration
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any
When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 22.2
The clock monitor automatically stops under the following conditions.
The clock monitor includes the following hardware.
• During oscillation stabilization time after STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit =
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU operates with the internal oscillation clock
0 during main clock operation)
Control register
Internal oscillation
Main clock
Item
clock
Figure 23-1. Timing of Reset via the RESET Pin Input
Table 23-1. Configuration of Clock Monitor
CHAPTER 23 CLOCK MONITOR
Clock monitor mode register (CLM)
Clock monitor mode
register (CLM)
Enable/disable
CLME
Configuration
CHAPTER 23 CLOCK MONITOR
Internal reset signal
Page 720 of 892
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