UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 9
UPD70F3744GJ-GAE-AX
Manufacturer Part Number
UPD70F3744GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3743GJ-GAE-AX.pdf
(911 pages)
Specifications of UPD70F3744GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3744GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 166
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 192
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 205
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6.1
6.2
6.3
6.4
6.5
4.3.12
4.3.13
4.3.14
4.3.15
Block Diagrams..................................................................................................................... 120
Port Register Settings When Alternate Function Is Used ................................................ 152
Cautions ................................................................................................................................ 161
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Features................................................................................................................................. 166
Bus Control Pins................................................................................................................... 167
5.2.1
5.2.2
Memory Block Function....................................................................................................... 168
External Bus Interface Mode Control Function ................................................................. 169
Bus Access ........................................................................................................................... 170
5.5.1
5.5.2
5.5.3
Wait Function ........................................................................................................................ 178
5.6.1
5.6.2
5.6.3
5.6.4
Idle State Insertion Function ............................................................................................... 182
Bus Hold Function................................................................................................................ 183
5.8.1
5.8.2
5.8.3
Bus Priority ........................................................................................................................... 185
Bus Timing ............................................................................................................................ 186
Overview................................................................................................................................ 192
Configuration ........................................................................................................................ 193
Registers ............................................................................................................................... 195
Operation............................................................................................................................... 200
6.4.1
6.4.2
PLL Function......................................................................................................................... 201
6.5.1
6.5.2
6.5.3
Port CS ....................................................................................................................................111
Port CT ....................................................................................................................................113
Port DH ....................................................................................................................................115
Port DL.....................................................................................................................................117
Cautions on setting port pins....................................................................................................161
Cautions on bit manipulation instruction for port n register (Pn)...............................................164
Cautions on on-chip debug pins...............................................................................................165
Cautions on P05/INTP2/DRST pin...........................................................................................165
Cautions on P53 pin when power is turned on.........................................................................165
Hysteresis characteristics ........................................................................................................165
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ...............167
Pin status in each operation mode...........................................................................................167
Number of clocks for access ....................................................................................................170
Bus size setting function ..........................................................................................................170
Access by bus size ..................................................................................................................171
Programmable wait function.....................................................................................................178
External wait function...............................................................................................................179
Relationship between programmable wait and external wait ...................................................180
Programmable address wait function.......................................................................................181
Functional outline.....................................................................................................................183
Bus hold procedure..................................................................................................................184
Operation in power save mode ................................................................................................184
Operation of each clock ...........................................................................................................200
Clock output function ...............................................................................................................200
Overview..................................................................................................................................201
Registers..................................................................................................................................201
Usage ......................................................................................................................................204
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