UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1002

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control
corresponding wait control, as shown below (n = 0 to 2).
1000
The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the
Notes 1.
Remarks 1. The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
WTIMn Bit
• Slave device operation: Interrupt and wait timing are determined according to the conditions described in
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
0
1
2.
2. n = 0 to 3 (V850ES/JH3-E)
The slave device’s INTIICn signal and wait period occur at the falling edge of the ninth clock only when
there is a match with the address set to the SVAn register.
At this point, the ACK is generated regardless of the value set to the IICCn.ACKEn bit. For a slave
device that has received an extension code, the INTIICn signal occurs at the falling edge of the eighth
clock.
When the address does not match after restart, the INTIICn signal is generated at the falling edge of the
ninth clock, but no wait occurs.
If the received address does not match the contents of the SVAn register and an extension code is not
received, neither the INTIICn signal nor a wait occurs.
and wait control are both synchronized with the falling edge of these clock signals.
n = 0 to 4 (V850ES/JJ3-E)
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 20-3. INTIICn Generation Timing and Wait Control
Data Reception
Notes 1 and 2 above, regardless of the WTIMn bit.
the WTIMn bit.
8
9
Note 2
Note 2
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
Data Transmission
8
9
Note 2
Note 2
2
C BUS
Address
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9